/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** **************************************************************************************
 * \file     Spi_PbCfg.c
 * \brief    AUTOSAR 4.3.1 MCAL can Driver
 *
 * <table>
 * <tr><th>Date           <th>Version
 * <tr><td>2025-04-17 12:17:59     <td>1.0.0 R
 * </table>
 *****************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************************
 *                       Include header files
 *****************************************************************************************/
#include "cdefs.h"
#include "Compiler.h"
#include "Spi_PbCfg.h"
#include "Mcal.h"
#include "regs_base.h"
/*****************************************************************************************
 *                   Global Macro definition
 *****************************************************************************************/
/** \brief  Spi UserCallback HeaderFile include */

#if (SPI_NO_CACHEABLE_NEEDED == STD_ON)
#define SPI_START_SEC_VAR_NO_INIT_NO_CACHE_UNSPECIFIED
#else
#define SPI_START_SEC_VAR_NO_INIT_UNSPECIFIED
#endif
#include "Spi_MemMap.h"

/* Channels params check */
                                                                                                                                            
/* Global array for internal write buffers */
/* Global array for internal read buffers */


#if (SPI_NO_CACHEABLE_NEEDED == STD_ON)
#define SPI_STOP_SEC_VAR_NO_INIT_NO_CACHE_UNSPECIFIED
#else
#define SPI_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#endif

#include "Spi_MemMap.h"

#define SPI_START_SEC_CONST_UNSPECIFIED
#include "Spi_MemMap.h"

/** \brief  This array contains configuration details for Channels */
CONST(Spi_ChannelCfgType, SPI_CONST) Spi_ChannelConfig[SPI_TOTAL_CH_COUNT] =
{
  /* Index: 0 - SpiChannel_0 */
  {
    /* channelBufferType */
    EB,
    /* dataWidth */
    8U,
    /* bufferSize */
    SPI_BUFFER_SIZE_CHANNEL_0,
    /* writeBufferIndex */
    NULL_PTR,
    /* readBufferIndex */
    NULL_PTR,
    /* bitOrder */
    MSB,
    /* defaultValue */
    0xFFU,
  }  ,
    /* Index: 1 - SpiChannel_1 */
  {
    /* channelBufferType */
    EB,
    /* dataWidth */
    8U,
    /* bufferSize */
    SPI_BUFFER_SIZE_CHANNEL_1,
    /* writeBufferIndex */
    NULL_PTR,
    /* readBufferIndex */
    NULL_PTR,
    /* bitOrder */
    MSB,
    /* defaultValue */
    0xFFU,
  }    
};

/* Channel list */
static  CONST(Spi_ChannelType, SPI_CONST) SpiJob_0_ChannelList [1]=
{
    /* Linked channels for job: 0  */
    0U,
};
static  CONST(Spi_ChannelType, SPI_CONST) SpiJob_1_ChannelList [1]=
{
    /* Linked channels for job: 1  */
    1U,
};
/*
  This array contains configuration details for Jobs.
  And sorted by Job priority
*/
                        


CONST(Spi_JobCfgType, SPI_CONST) Spi_JobConfig[SPI_TOTAL_JOB_COUNT] =
{
    /* Index: 0 - SpiJob_0 */
  {
    /* DataWith */
    8,
    /* bitOrder */
    MSB,
    /* device Idx */
    0,
    /*hwIdxOfHwUnitCfgs*/
    0U,
    /* hwUnitId */
    CSIB2,
    /* CSIdx */
    /** Traceability       : SWSR_SPI_010 */
    SPI_CS_3,
    /* GPIOCsPinID*/
    0xFF,
    /* IsEnableRx */
    FALSE,
    /* CSHandling */
    CS_VIA_PERIPHERAL_ENGINE,
    /* CSPolarity */
    (uint8)LOW,
    /** Traceability       : SWSR_SPI_003 */
    /* baudRateDiv Div  rootclk is 100000000M */
    49U,
    /* timeClk2Cs StartDelay */
    0U,    
    /* EndDelay */
    0U,    
    /* Frame delay */
    0U,    
    /* Job delay */
    0U,    
    /* idleLevel */
    LOW,
    /* shiftEdge */
    LEADING,
    /* config the parity of transmission */
    SPI_P_NONE,
    /* Priority */
    0U,
    /* jobEndNotification */
    NULL_PTR,
    /* numOfChannels */
    1U,
    /* ChannelList */
    SpiJob_0_ChannelList,
    /* In master mode, delay half sclk to sample miso */
    0,
    /* In master mode, swap BE32 or BE16 to LE32 or LE16 */
    FALSE,
    /* In master mode, the transmission timeout protect  */
    31,
  },
    /* Index: 1 - SpiJob_1 */
  {
    /* DataWith */
    8,
    /* bitOrder */
    MSB,
    /* device Idx */
    1,
    /*hwIdxOfHwUnitCfgs*/
    0U,
    /* hwUnitId */
    CSIB2,
    /* CSIdx */
    /** Traceability       : SWSR_SPI_010 */
    SPI_CS_5,
    /* GPIOCsPinID*/
    0xFF,
    /* IsEnableRx */
    FALSE,
    /* CSHandling */
    CS_VIA_PERIPHERAL_ENGINE,
    /* CSPolarity */
    (uint8)LOW,
    /** Traceability       : SWSR_SPI_003 */
    /* baudRateDiv Div  rootclk is 100000000M */
    49U,
    /* timeClk2Cs StartDelay */
    0U,    
    /* EndDelay */
    0U,    
    /* Frame delay */
    0U,    
    /* Job delay */
    0U,    
    /* idleLevel */
    LOW,
    /* shiftEdge */
    LEADING,
    /* config the parity of transmission */
    SPI_P_NONE,
    /* Priority */
    0U,
    /* jobEndNotification */
    NULL_PTR,
    /* numOfChannels */
    1U,
    /* ChannelList */
    SpiJob_1_ChannelList,
    /* In master mode, delay half sclk to sample miso */
    0,
    /* In master mode, swap BE32 or BE16 to LE32 or LE16 */
    FALSE,
    /* In master mode, the transmission timeout protect  */
    31,
  },
};

/* Job list */

static CONST(Spi_JobType, SPI_CONST) SpiSequence_0_JobList [1]=
{
    /*
      Linked Job for Sequence: 0
      and sorted by Job priority.
    */
    0U ,  
};

static CONST(Spi_JobType, SPI_CONST) SpiSequence_1_JobList [1]=
{
    /*
      Linked Job for Sequence: 1
      and sorted by Job priority.
    */
    1U ,  
};






/* This array contains configuration details for Sequences */
CONST(Spi_SequenceCfgType, SPI_CONST) Spi_SequenceConfig[SPI_TOTAL_SEQ_COUNT] =
{
  /* Index: 0 - SpiSequence_0 */
  {
    /* interruptableSequence */
    FALSE,
    /* sequenceEndNotification */
    NULL_PTR,
    /* numOfJobs */
    1U,
    /* JobList */
    SpiSequence_0_JobList,
    /* Jobs HwMask */
    (0x1U << CSIB2)
  },
  /* Index: 1 - SpiSequence_1 */
  {
    /* interruptableSequence */
    FALSE,
    /* sequenceEndNotification */
    NULL_PTR,
    /* numOfJobs */
    1U,
    /* JobList */
    SpiSequence_1_JobList,
    /* Jobs HwMask */
    (0x1U << CSIB2)
  },

};

/*PRQA S 0686,1533 110*/
/* Hw list */
/* This array contains HwUnit property */
CONST(Spi_HwUnitConfigType, SPI_CONST) Spi_HwUnitConfig[SPI_TOTAL_HW_COUNT] =
{
  
  /* SpiHwUnit_0 */
  {
    .hwUnitId = CSIB2,
    /* DMA mode Enable */
    .isEnableDMA = (boolean)FALSE,
    /* hwMode: spi master or slave */
    .hwMode = SPI_MASTER,
    /* Ti mode Enable */
    .isEnableTiMod = (boolean)FALSE,
    /* In E3 this params no use */
    .transferMode = SPI_ASYNC_MODE,
    /* controler base */
    .ctrlRegBase = APB_SPI2_BASE,
  }
};


CONST(uint32, SPI_CONST) Spi_InstanceMask_Config[5] =
{
  
    (0x1U << CSIB2) |     0U,0U,0U,0U,0U
  
};
/** \brief  Structure for SPI Init configuration */
/** Traceability       : SWSR_SPI_007 SWSR_SPI_086 */
CONST(Spi_ConfigType, SPI_CONST) Spi_Config[SPI_TOTAL_DRIVERS] =
{
  /* Index: 0 - SpiDriver */
  {
    /* ChannelType */
    Spi_ChannelConfig,
    /* JobType */
    Spi_JobConfig,
    /* SequenceType */
    Spi_SequenceConfig
  }
};

#define SPI_STOP_SEC_CONST_UNSPECIFIED
#include "Spi_MemMap.h"

#ifdef __cplusplus
}
#endif
/* End of file */


